1. Field of the Invention
The present invention relates to the field of processors and more particularly to translation lookaside buffers within processors.
2. Description of the Related Art
In computer systems it is known for a processor to have a cache memory to speed up memory access operations to main memory of the computer system. The cache memory is smaller, but faster than main memory. It is placed operationally between the processor and main memory. During the execution of a software program, the cache memory stores more frequently used instructions and data. Whenever the processor needs to access information from main memory, the processor examines the cache first before accessing main memory. A cache miss occurs if the processor cannot find instructions or data in the cache memory and is required to access the slower main memory. Thus, the cache memory reduces the average memory access time of the processor.
In known computer systems, it is common to have a process executing only in main memory (“physical memory”) while a programmer or user perceives a much larger memory which is allocated on an external disk (“virtual memory”). Virtual memory allows for very effective multi-programming and relieves the user of potential constraints associated with the main memory. To address the virtual memory, many processors contain a translator to translate virtual addresses in virtual memory to physical addresses in physical memory, and a translation lookaside buffer (“TLB”), which caches recently generated virtual-physical address pairs. The TLBs allow faster access to main memory by skipping the mapping process when the translation pairs already exist. A TLB entry is like a cache entry where a tag includes portions of the virtual address and a data portion includes a physical page frame number.
One aspect of processor performance relates to monitoring certain addresses such as instruction addresses via, for example, a watchpoint address or a sample address range. When monitoring the instruction address, it becomes important to quickly compare the instruction address against the watchpoint address or the sample address range. When a match is detected between the instruction address and the monitoring address, the processor takes some sort of action such as generating a watchpoint trap if the address matches the watchpoint address or collecting sampling information if the instruction address is within the sample address range.